Digital Design Engineer (3+ Years Experience)

ABOUT THE ROLE

We are looking for an experienced Digital Design Engineer to join our IC design team in Thessaloniki. In this role, you will take full ownership of digital block design from microarchitecture definition through RTL implementation and front-end sign-off, working closely with verification, analog, and physical design teams to deliver custom ASICs and SoC subsystems from specification to tape-out.

KEY RESPONSIBILITIES

• Define microarchitecture and implement digital blocks and SoC subsystems at RTL level using Verilog and/or SystemVerilog
• Design and integrate RISC-V processor cores and high-speed peripheral interfaces
• Perform logic synthesis targeting advanced process nodes (28nm/14nm) and drive PPA optimization
• Run front-end sign-off including lint (zero-violation), CDC/RDC analysis using industry-standard tools (e.g., Spyglass, Meridian), and logic equivalence checking (LEC)
• Define and apply timing constraints and drive static timing analysis (STA) closure
• Collaborate with verification teams to define test plans and support functional sign-off
• Collaborate with backend teams to ensure successful physical implementation
• Apply safety-aware design practices in accordance with functional safety requirements where applicable
• Support silicon bring-up, debug, and root cause analysis of hardware failures
• Participate in design reviews and contribute to technical documentation

REQUIRED QUALIFICATIONS

• MSc or PhD in Electrical/Electronic Engineering, Computer Engineering, or related field
• 3+ years of industry experience in digital ASIC or SoC design
• Strong proficiency in RTL design using Verilog and/or SystemVerilog
• Proven experience with the complete ASIC digital front-end flow including synthesis, STA, LEC, lint, and CDC
• Strong knowledge of SoC architectures and bus protocols (AXI, AHB, APB)
• Proficiency in clock domain crossing (CDC) and reset domain crossing (RDC) techniques and sign-off flows
• Experience with industry-standard EDA tools (e.g., Synopsys Design Compiler, Cadence Genus/Tempus, Spyglass)
• Familiarity with scripting languages for design automation (e.g., Python, TCL, Perl)
• Understanding of low-power design techniques and UPF-based flows

PREFERRED QUALIFICATIONS

• Experience with RISC-V ISA or processor microarchitecture design
• Knowledge of functional safety standards and safety-critical design practices (e.g., ISO 26262)
• Familiarity with DFT concepts and scan insertion flows
• Experience with formal verification techniques
• Exposure to mixed-signal design environments and co-simulation flows
• Knowledge of advanced CMOS process nodes (28nm/14nm and below) and their impact on digital design
• Familiarity with FPGA prototyping flows

KEY COMPETENCIES

• Strong microarchitecture intuition and ability to translate specifications into efficient RTL
• Deep understanding of the impact of design decisions on timing, area, and power
• Ownership-driven mindset with accountability for block quality from spec to tape-out
• Rigorous approach to design quality with zero-tolerance for lint and CDC violations
• Ability to anticipate implementation challenges early in the design cycle
• Clear and precise documentation of design intent and microarchitecture decisions
• Collaborative attitude with physical design and verification teams without losing design ownership