Digital Verification Engineer (3+ Years Experience)

ABOUT THE ROLE

We are looking for an experienced Digital Verification Engineer to join our design team in Thessaloniki. In this role, you will take full ownership of verification from plan to sign-off across block, subsystem, and full-chip levels, working closely with digital and analog design teams to ensure first-pass silicon success on custom ASIC and SoC designs.

KEY RESPONSIBILITIES

• Develop comprehensive verification plans and strategies for complex SoC/ASIC designs
• Architect and implement modular, scalable UVM-based testbenches including drivers, monitors, and scoreboards
• Define and achieve functional and code coverage targets to ensure design robustness before tape-out
• Perform gate-level simulation (GLS) and power-aware verification (UPF) for advanced process nodes
• Apply formal verification techniques to prove correctness of critical blocks and control logic
• Debug and triage complex design failures at block, subsystem, and full-chip levels
• Support mixed-signal verification at the analog-digital interface, particularly for advanced process nodes
• Collaborate with design and architecture teams to enforce design-for-verification (DFV) best practices
• Support post-silicon validation by adapting and re-running verification test cases on hardware
• Participate in design reviews and contribute to technical documentation

REQUIRED QUALIFICATIONS

• MSc or PhD in Electrical/Electronic Engineering, Computer Science, or related field
• 3+ years of industry experience in digital ASIC or SoC verification
• Extensive experience with SystemVerilog and UVM including testbench architecture from scratch
• Proficiency in scripting languages for regression automation (e.g., Python, Perl, TCL)
• Hands-on experience with industry-standard simulators (e.g., Synopsys VCS, Cadence Xcelium, Mentor Questa)
• Familiarity with RISC-V architecture and AMBA bus protocols (AXI, AHB, APB)
• Experience with CDC/RDC verification and low-power sign-off flows (UPF)
• Fluency in English, minimum C1 level (oral and written)
• Greek, EU, or Schengen area citizen, or holder of a valid Greek work permit

PREFERRED QUALIFICATIONS

• Experience with formal verification tools (e.g., JasperGold, VC Formal) for property checking and coverage closure
• Familiarity with fault simulation and safety verification flows in the context of functional safety (ISO 26262)
• Experience with hardware emulation platforms (e.g., Cadence Palladium, Synopsys ZeBu) or FPGA prototyping
• Knowledge of SystemVerilog Assertions (SVA) and assertion-based verification methodologies
• Exposure to mixed-signal co-simulation environments (e.g., Verilog-AMS, SV-RNM)
• Familiarity with off-the-shelf Verification IPs (VIPs) for standard protocols
• Experience with lint and static analysis flows as part of a zero-violation sign-off culture

KEY COMPETENCIES

• Adversarial mindset with a systematic approach to finding design bugs before silicon
• Deep understanding of coverage-driven verification and ability to identify and close coverage holes
• Ability to architect scalable and reusable testbench environments from scratch
• Rigorous approach to sign-off metrics with a zero-tolerance mindset for unresolved coverage gaps
• Structured approach to regression management and verification sign-off tracking
• Clear documentation of verification plans, results, and escape analysis
• Collaborative attitude with design teams while maintaining independent verification judgment