SerDes / High-Speed I/O IC Design Engineer (3+ years Experience)

ABOUT THE ROLE

We are looking for an experienced SerDes and High-Speed I/O Design Engineer to join our analog design team in Thessaloniki. In this role, you will be responsible for the design and development of high-speed serializer/deserializer blocks and associated I/O circuits targeting industry-standard protocols such as PCIe, USB, MIPI, and Ethernet. This is an opportunity to work on cutting-edge high-speed interfaces for custom ASIC and SoC platforms, collaborating closely with digital, verification, and system teams to deliver silicon-proven solutions.

KEY RESPONSIBILITIES

• Design and develop high-speed SerDes blocks including TX drivers, RX front-ends, clock and data recovery (CDR), and equalizers (FFE, DFE, CTLE)
• Implement and optimize PLLs, DLLs, and clock generation circuits for high-speed interfaces
• Design I/O circuits targeting industry-standard protocols including PCIe, USB, MIPI, Ethernet (SGMII, XFI, 25G/100G), SATA, DisplayPort, and HDMI
• Perform system-level modeling and simulation to define jitter budgets and link performance using MATLAB or SystemVerilog
• Perform signal integrity analysis, eye diagram simulation, and jitter characterization
• Conduct transistor-level simulation including noise, mismatch, Monte Carlo, and PVT corners
• Supervise layout and post-layout verification with focus on parasitic extraction and signal integrity in deep sub-micron nodes
• Collaborate with digital teams on PCS/PMA interface definition, mixed-signal integration, and full-chip integration
• Define block and interface specifications in coordination with system architects
• Support silicon bring-up, characterization, and compliance testing
• Participate in design reviews and contribute to technical documentation

REQUIRED QUALIFICATIONS

• MSc or PhD in Electrical/Electronic Engineering or related field
• 3+ years of industry experience in analog/mixed-signal IC design with focus on high-speed I/O or SerDes
• Solid understanding of SerDes architecture including CDR, equalization, and jitter budget
• Experience with PLL/DLL design and clock distribution
• Proficiency with transistor-level simulation in SPICE-based environments (Cadence Virtuoso, SpectreRF)
• Strong understanding of transmission line effects, impedance matching, and signal integrity
• Deep understanding of device physics, noise analysis, and layout matching in advanced CMOS nodes
• Familiarity with one or more high-speed protocols (PCIe, USB, Ethernet, MIPI, SATA, etc.)
• Familiarity with physical verification tools (Calibre)

PREFERRED QUALIFICATIONS

• Experience with analog layout for high-speed circuits including shielding, return path management, and parasitic-aware design
• Familiarity with DRC/LVS flows and analog sign-off tools
• Exposure to IBIS or S-parameter modeling and channel simulation tools
• Experience with compliance testing and protocol certification flows
• Familiarity with scripting for simulation automation (e.g., Python, SKILL, TCL)
• Knowledge of advanced CMOS nodes (28nm/14nm and below) and their impact on high-speed design

KEY COMPETENCIES

• Deep understanding of high-frequency analog circuit behavior
• Strong signal integrity and system-level thinking
• Methodical simulation and debug approach across frequency and time domains
• Clear technical communication and documentation skills
• Collaborative mindset across analog, digital, and system teams